Semiconductor device and fabrication method thereof

ABSTRACT

A semiconductor device includes a barrier layer, a dielectric layer, a first spacer, a second spacer, and a gate. The dielectric layer is disposed on the barrier layer and defines a first recess. The first spacer is disposed on the barrier layer and within the first recess. The second spacer is disposed on the barrier layer and within the first recess. The first and second spacers are spaced apart from each other by a top surface of a portion of the barrier layer. The top surface of the portion of the barrier layer is recessed. The gate is disposed on the barrier layer, the dielectric layer, and the first and second spacers, in which the gate has a bottom portion located between the first and second spacers and making contact with the top surface of the portion of the barrier layer.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a continuation application of U.S. application Ser. No. 16/771,670, filed as national phase entry on 10 Jun. 2020, which is national phase entry of the International Patent Application No. PCT/CN2020/081115 filed on Mar. 25, 2020, which claims priority from the China Patent Application No. 201910245261.2 filed on Mar. 28, 2019, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND 1. Technical Field

The present disclosure relates to a semiconductor device, and more particularly to a high electron mobility semiconductor device and a fabrication method thereof.

2. Description of the Related Art

A high electron mobility transistor (HEMT) is a kind of field effect transistor. Unlike metal oxide semiconductor (MOS) field-effect transistors, the HEMT uses two materials with different energy gaps to form a heterojunction. The polarization of heterojunction forms a two-dimensional electron gas (2DEG) region in the channel layer, providing a channel for carriers. The HEMT attracts a lot of attention because of its high frequency characteristics. Because it can work at high frequencies, it is widely used in various radio frequency (RF) devices or mobile devices.

In the RF applications, the gate profile of a HEMT may affect the frequency characteristics and/or performance of the HEMT. In order to manufacture a HEMT that has a desired gate profile, machines having specific precision requirements may be necessary and thus may result in high manufacturing costs. Therefore, there is a need to provide a semiconductor device and a fabrication method thereof to resolve the above issue.

SUMMARY OF THE INVENTION

In some embodiments of the present disclosure, a semiconductor device is provided. The semiconductor device includes a barrier layer, a dielectric layer, a first spacer, a second spacer, and a gate. The dielectric layer is disposed on the barrier layer and defines a first recess. The first spacer is disposed on the barrier layer and within the first recess. The second spacer is disposed on the barrier layer and within the first recess. The first and second spacers are spaced apart from each other by a top surface of a portion of the barrier layer. The top surface of the portion of the barrier layer is recessed. The gate is disposed on the barrier layer, the dielectric layer, and the first and second spacers, in which the gate has a bottom portion located between the first and second spacers and making contact with the top surface of the portion of the barrier layer.

In some embodiments of the present disclosure, a semiconductor structure is provided. The semiconductor device includes a barrier layer, a first spacer, a second spacer, a dielectric layer, and a gate. The barrier layer has a top surface and a first recess at the top surface. The first spacer is disposed on the barrier layer and adjacent to the first recess. The second spacer is disposed on the barrier layer and adjacent to the first recess, in which the first recess is located between the first and second spacers. The dielectric layer is disposed on the barrier layer and away from the first recess such that the first and second spacers are closer to the first recess than the dielectric layer. The gate is disposed over the barrier layer, the dielectric layer, and the spacer. The gate has a first portion extending from the first recess to the dielectric layer along the first spacer and a second portion extending from the first recess to the dielectric layer along the second spacer, such that the gate has a second recess between the first and second portions and over the first recess.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1A is a simplified schematic cross-sectional view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 1B is a simplified schematic cross-sectional view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 1C is an enlarged view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 1D is an enlarged view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 1E is an enlarged view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 1F is a simplified schematic cross-sectional view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 1G is a simplified schematic cross-sectional view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 2A is a simplified schematic cross-sectional view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 2B is an enlarged view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 2C is an enlarged view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 2D is an enlarged view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D and FIG. 3E illustrate a method of manufacturing a semiconductor structure according to some embodiments of the present disclosure.

FIG. 3F is a top view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 3G is a top view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E and FIG. 4F illustrate a method of manufacturing a semiconductor structure according to some embodiments of the present disclosure.

FIG. 5 is a simplified schematic cross-sectional view of a portion of a semiconductor structure according to certain comparative embodiments of the present disclosure.

FIG. 6 is a simplified schematic cross-sectional view of a portion of a semiconductor structure according to certain comparative embodiments of the present disclosure.

PREFERRED EMBODIMENT OF THE PRESENT INVENTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. In the present disclosure, reference to the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

In field effect transistors (FETs), depletion mode (D-mode) and enhancement mode (E-mode) are two major transistor types, corresponding to whether the transistor is in an ON state or an OFF state at zero gate bias voltage.

A depletion mode HEMT is conductive at zero gate bias voltage, due to the polarization-induced charge at the barrier/channel interface, and is also known as depletion HEMT, or dHEMT. A dHEMT is a normally-on device and is suitable for applications involving, for example, radio communications, radio frequency (RF) devices, RF power amplifiers, and/or microwave devices.

A HEMT made of semiconductor hetero-interfaces lacking interfacial net polarization charge (such as AlGaAs/GaAs), requires positive gate voltage or appropriate donor-doping in the AlGaAs barrier to attract the electrons towards the gate, which forms the 2D electron gas and enables conduction of electron currents. This behavior is similar to that of commonly used field-effect transistors in the E-mode, and such a device is called enhancement HEMT, or eHEMT. An eHEMT is a normally-off device and is suitable for applications involving, for example, power controlling and circuit controlling.

FIG. 1A is a simplified schematic cross-sectional view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 1A shows a semiconductor structure 100 according to certain embodiments of the present disclosure. The semiconductor structure 100 can also be referred to as a semiconductor device or a semiconductor apparatus.

As shown in FIG. 1A, the semiconductor structure 100 includes a substrate 10, a channel layer 12, a barrier layer 14, a dielectric layer 16, a gate 20, a drain 22 and a source 24. The semiconductor structure 100 further includes spacers 18 a and 18 b.

The substrate 10 may include, without limitation, silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), or other semiconductor materials. The substrate 10 may include, without limitation, sapphire, silicon on insulator (SOI), or other suitable materials. In some embodiments, the substrate 10 may further include a doped region (not shown in FIG. 1A), for example, a p-well, n-well, or the like.

The channel layer 12 can be disposed on the substrate 10. The channel layer 12 may contain, for example, but is not limited to, group III nitrides, such as compound Al_(y)Ga_((1-y))N, where y≤1. In some embodiments, the channel layer 12 may include GaN. In some embodiments, the channel layer 12 may include undoped GaN. In some embodiments, the channel layer 12 may include doped GaN.

The barrier layer 14 can be disposed on the channel layer 12. The barrier layer 14 may contain, for example, but is not limited to, group III nitrides, such as compound Al_(y)Ga_((1-y))N, where y≤1. The barrier layer 14 may have a relatively larger bandgap than the channel layer 12. In some embodiments, the barrier layer 14 may include AlGaN. In some embodiments, the barrier layer 14 may include undoped AlGaN. In some embodiments, the barrier layer 14 may include doped AlGaN.

The channel layer 12 and the barrier layer 14 may include, without limitation, for example, a p-type dopant, an n-type dopant, or other dopants. In some embodiments, exemplary dopants can include, for example, but are not limited to, magnesium (Mg), zinc (Zn), cadmium (Cd), silicon (Si), germanium (Ge), and the like.

Heterojunction can be formed between the channel layer 12 and the barrier layer 14. The polarization resulting from the heterojunction between different nitrogen compounds forms a 2DEG region 13. In some embodiments, the 2DEG region 13 is formed within the channel layer 12. In some embodiments, the 2DEG region 13 is formed adjacent to the interface between the channel layer 12 and the barrier layer 14. In some embodiments, the 2DEG region 13 is formed in a layer with a small band gap (e.g. GaN).

The channel layer 12 can supply electrons to the 2DEG region. The channel layer 12 can remove electrons from the 2DEG region. The channel layer 12 can control the conduction of the semiconductor structure 100 with high electron mobility.

The dielectric layer 16 can be disposed on the barrier layer 14. In some embodiments, the dielectric layer 16 may include a multi-layered structure. In some embodiments, the dielectric layer 16 may include several stacked dielectric layers of different materials.

The dielectric layer 16 may include, without limitation, for example, an oxide or a nitride, such as silicon nitride (SiN), silicon oxide (SiO₂), and the like. The dielectric layer 16 may include, for example, without limitation, a composite layer of an oxide and a nitride, such as Al₂O₃/SiN, Al₂O₃/SiO₂, AlN/SiN, AlN/SiO₂, and the like.

The spacers 18 a and 18 b can be disposed within a recess of the dielectric layer 16. The spacers 18 a and 18 b may include dielectric materials. The spacers 18 a and 18 b may include, without limitation, for example, an oxide or a nitride, such as silicon nitride (SiN), silicon oxide (SiO₂), and the like. The spacers 18 a and 18 b may include, for example, without limitation, a composite layer of an oxide and a nitride, such as Al₂O₃/SiN, Al₂O₃/SiO₂, AlN/SiN, AlN/SiO₂, and the like.

In some embodiments, the spacers 18 a and 18 b may include materials identical to those of the dielectric layer 16. In some embodiments, the spacer 18 a may be referred to as a part of the dielectric layer 16. In some embodiments, the spacer 18 b may be referred to as a part of the dielectric layer 16. In some embodiments, the spacers 18 a and 18 b may include materials different from those of the dielectric layer 16.

In some embodiments, each of the spacers 18 a and 18 b can be a portion of an overall spacer (for example, the spacer 181 shown in FIG. 3G). In some embodiments, each of the spacers 18 a and 18 b can be referred to as a portion of a spacer.

An interface 14 i exists between the spacer 18 a and the barrier layer 14. An interface 16 i 1 exists between the spacer 18 a and the dielectric layer 16. An interface 16 i 2 exists between the spacer 18 b and the dielectric layer 16. An interface 18 i 1 exists between the spacer 18 a and the gate 20. An interface 18 i 2 exists between the spacer 18 b and the gate 20. In some embodiments, the interfaces 14 i and 16 i may be substantially flat surfaces. In some embodiments, the interfaces 18 i 1 and 18 i 2 may be curved surfaces. The interface 18 i 1 can also be referred to as an upper surface of the spacer 18 a. The interface 18 i 2 can also be referred to as an upper surface of the spacer 18 b.

A length L1 represents the distance between the interface 16 i 1 and the interface 16 i 2. The length L1 represents the gap or the recess of the dielectric layer 16. The length L1 can also be referred to as a width L1. A length L2 represents the smallest distance between the spacer 18 a and the spacer 18 b. The length L2 can also be referred to as a width L2. Referring to FIG. 1A, the length L2 is smaller than the length L1.

The length L1 can be larger than 250 nanometers (nm). In some embodiments, the length L1 can be, for example, around 300 nm. The length L2 can be less than 140 nm. The length L2 can be in a range of 120 nm to 140 nm. The length L2 can be in a range of 100 nm to 120 nm. The length L2 can be in a range of 80 nm to 100 nm. The length L2 can be in a range of 60 nm to 80 nm. The length L2 can be in a range of 40 nm to 60 nm. In some embodiments, the length L2 can be, for example, around 120 nm.

The drain 22 and the source 24 can be disposed on the dielectric layer 16. In some embodiments, the drain 22 and the source 24 may include, for example, but are not limited to, conductive materials. Conductive materials may include, but are not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon) or other suitable conductor materials.

The gate 20 can be disposed on the spacers 18 a and 18 b. The gate 20 may cover the spacers 18 a and 18 b. The gate 20 can be disposed on the dielectric layer 16. The gate 20 may cover a portion of the dielectric layer 16. The gate 20 may expose a portion of the dielectric layer 16.

A portion of the gate 20 can be disposed within the recess defined by the spacers 18 a and 18 b. The portion of the gate disposed between the spacers 18 a and 18 b may be referred to as a tapered portion. The term “tapered” in the present disclosure may means an object having a shape that gets narrower towards one end.

The gate 20 may include a recess 20 r. The gate 20 may include curved surfaces 20 s 1 and 20 s 2. The recess 20 r can be defined by the curved surfaces 20 s 1 and 20 s 2. The surface 20 s 1 can be a convex surface. The surface 20 s 2 can be a convex surface. The dimension of the recess 20 r decreases gradually in a direction toward the barrier layer 14.

In some embodiments, a portion of the gate 20 can be conformally disposed in accordance with the interface 18 i 1. In some embodiments, a portion of the gate 20 can be conformally disposed in accordance with the interface 18 i 2. In some embodiments, the surface 20 s 1 may include a curvature similar to that of the interface 18 i 1. In some embodiments, the surface 20 s 2 may include a curvature similar to that of the interface 18 i 2.

A portion of the gate 20 can be spaced apart from the dielectric layer 16. A portion of the gate 20 can be spaced apart from the barrier layer 14. A portion of the gate 20 may not contact the dielectric layer 16. A portion of the gate 20 may not contact the barrier layer 14.

In some embodiments, a portion of the gate 20 between the surface 20 s 1 and the interface 18 i 1 can be spaced apart from the dielectric layer 16. In some embodiments, a portion of the gate 20 between the surface 20 s 1 and the interface 18 i 1 can be spaced apart from the barrier layer 14. In some embodiments, a portion of the gate 20 between the surface 20 s 2 and the interface 18 i 2 can be spaced apart from the dielectric layer 16. In some embodiments, a portion of the gate 20 between the surface 20 s 2 and the interface 18 i 2 can be spaced apart from the barrier layer 14.

In some embodiments, a portion of the gate 20 can be laterally spaced apart from the dielectric layer 16. In some embodiments, a portion of the gate 20 can be laterally spaced apart from the dielectric layer 16 by the spacer 18 a. In some embodiments, a portion of the gate 20 between the surface 20 s 1 and the interface 18 i 1 can be laterally spaced apart from the dielectric layer 16 by the spacer 18 a.

In some embodiments, a portion of the gate 20 can be laterally spaced apart from the dielectric layer 16 by the spacer 18 b. In some embodiments, a portion of the gate 20 between the surface 20 s 2 and the interface 18 i 2 can be laterally spaced apart from the dielectric layer 16 by the spacer 18 b.

The gate 20 may include a stacked gate dielectric layer (not shown) and gate metal. The gate dielectric layer may include one or more layers of dielectric materials, such as silicon oxide, silicon nitride, high dielectric constant dielectric materials or other suitable dielectric materials. Gate metal may include, for example, but is not limited to, titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), molybdenum (Mo) and its compounds (but not limited to, for example, titanium nitride (TiN), tantalum nitride (TaN) and other conductive nitrides, or conductive oxides), the metal alloy (such as aluminum copper alloy (Al—Cu)), or other appropriate material.

FIG. 1B is a simplified schematic cross-sectional view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 1B shows a semiconductor structure 200 according to certain embodiments of the present disclosure. The semiconductor structure 200 can also be referred to as a semiconductor device or a semiconductor apparatus.

The semiconductor structure 200 shown in FIG. 1B is similar to the semiconductor structure 100 shown in FIG. 1A, except that the barrier layer 14 of the semiconductor structure 200 includes a recess 14 r. The recess 14 r may result from the etching process during the manufacturing of the semiconductor structure 200.

An enlarged view of the portion enclosed by the dotted rectangle A shown in FIG. 1B will be discussed in accordance with FIG. 1C. An enlarged view of the portion enclosed by the dotted rectangle B shown in FIG. 1B will be discussed in accordance with FIGS. 1D and 1E.

FIG. 1C is an enlarged view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 1C shows a portion of the semiconductor structure 200. Referring to FIG. 1C, the bottom of the recess 14 r may include portions 20 i 1, 20 i 2 and 20 i 3. The portions 20 i 1, 20 i 2 and 20 i 3 are continuously connected. In some embodiments, the bottom of the recess 14 r may include more than three portions that are continuously connected. In some embodiments, the bottom of the recess 14 r may include fewer portions.

The portion 20 i 1 is lower than the interface 14 i between the spacer 18 a and the barrier layer 14. The portion 20 i 1 is not coplanar with the interface 14 i between the spacer 18 a and the barrier layer 14. In some embodiments, the portion 20 i 1 can be an inclined surface of the barrier layer 14.

The portion 20 i 2 is lower than the interface 14 i between the spacer 18 a and the barrier layer 14. The portion 20 i 2 is not coplanar with the interface 14 i between the spacer 18 a and the barrier layer 14. In some embodiments, the portion 20 i 2 can be a horizontal surface of the barrier layer 14.

The portion 20 i 3 is lower than the interface 14 i between the spacer 18 a and the barrier layer 14. The portion 20 i 3 is not coplanar with the interface 14 i between the spacer 18 a and the barrier layer 14. In some embodiments, the portion 20 i 3 can be an inclined surface of the barrier layer 14.

A depth D1 exists between the shallowest part of the portion 20 i 1 and the interface 14 i. A depth D2 exists between the portion 20 i 2 and the interface 14 i. In some embodiments, the depth D2 is greater than the depth D1.

FIG. 1D is an enlarged view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 1D shows a portion of the semiconductor structure 200 according to certain embodiments of the present disclosure. Referring to FIG. 1D, the interface 18 i 2 between the spacer 18 b and the gate 20 may be a relatively rough surface. The surface 16 s of the dielectric layer 16 may be a relatively rough surface. The relatively rough interface 18 i 2 can result from the etching process during the manufacturing of the semiconductor structure 200. The relatively rough surface 16 s can result from the etching process during the manufacturing of the semiconductor structure 200.

FIG. 1E is an enlarged view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 1E shows a portion of the semiconductor structure 200 according to certain embodiments of the present disclosure. The spacer 18 b shown in FIG. 1E includes a portion 18 b′ extending on the surface 16 s of the dielectric layer 16. The portion 18 b′ can result from the etching process during the manufacturing of the semiconductor structure 200.

The interface 18 i 2 between the spacer 18 b and the gate 20 may be a relatively rough surface. The relatively rough interface 18 i 2 can result from the etching process during the manufacturing of the semiconductor structure 200.

FIG. 1F is a simplified schematic cross-sectional view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 1F shows a semiconductor structure 100′ according to certain embodiments of the present disclosure. The semiconductor structure 100′ can also be referred to as a semiconductor device or a semiconductor apparatus.

As shown in FIG. 1F, the semiconductor structure 100′ includes a substrate 10, a channel layer 12, a barrier layer 14, a dielectric layer 16, a gate 20, a drain 22 and a source 24. The semiconductor structure 100′ further includes spacers 18 a and 18 b. The semiconductor structure 100′ shown in FIG. 1F is similar to the semiconductor structure 100 shown in FIG. 1A, except that the spacers 18 a and 18 b and the gate 20 of the semiconductor structure 100′ have different profiles.

Referring to FIG. 1F, the spacer 18 a includes a sidewall 18 w 1, and the spacer 18 b includes a sidewall 18 w 2. The sidewall 18 w 1 can also be referred to as a surface. The sidewall 18 w 2 can also be referred to as a surface. The sidewall 18 w 1 can also be referred to as an interface between the spacer 18 a and the gate 20. The sidewall 18 w 2 can also be referred to as an interface between the spacer 18 b and the gate 20.

The sidewall 18 w 1 can be an inclined surface. The sidewall 18 w 2 can be an inclined surface. The sidewall 18 w 1 can be a relatively rough surface. The sidewall 18 w 2 can be a relatively rough surface. The sidewall 18 w 1 comes gradually closer toward the sidewall 18 w 2. The sidewall 18 w 2 comes gradually closer toward the sidewall 18 w 1.

The gate 20 includes a recess 20 r. The gate 20 includes a surface 20 s 1 and a surface 20 s 2. The slope of the surface 20 s 1 may be substantially identical to that of the sidewall 18 w 1. The slope of the surface 20 s 2 may be substantially identical to that of the sidewall 18 w 2. The gate 20 includes a tapered portion between the spacers 18 a and 18 b. The gate 20 includes a tapered portion in the recess defined by the sidewall 18 w 1, the side wall 18 w 2 and the exposed surface of the barrier layer 14.

FIG. 1G is a simplified schematic cross-sectional view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 1G shows a semiconductor structure 100″ according to certain embodiments of the present disclosure. The semiconductor structure 100″ can also be referred to as a semiconductor device or a semiconductor apparatus.

As shown in FIG. 1G, the semiconductor structure 100″ includes a substrate 10, a channel layer 12, a barrier layer 14, a dielectric layer 16, a gate 20, a drain 22 and a source 24. The semiconductor structure 100″ further includes spacers 18 a and 18 b. The semiconductor structure 100″ shown in FIG. 1G is similar to the semiconductor structure 100 shown in FIG. 1A, except that the spacers 18 a and 18 b and the gate 20 of the semiconductor structure 100″ have different profiles.

The spacer 18 a includes a step structure defined by sidewalls 18 w 1 and 18 w 2. The spacer 18 a further includes another step structure defined by sidewalls 18 w 3 and 18 w 4. The spacer 18 b includes a step structure defined by sidewalls 18 w 5 and 18 w 6. The spacer 18 b further includes another step structure defined by sidewalls 18 w 7 and 18 w 8. Each of the sidewalls 18 w 1, 18 w 2, 18 w 3, 18 w 4, 18 w 5, 18 w 6, 18 w 7 and 18 w 8 can also be referred to as a surface. Each of the sidewalls 18 w 1, 18 w 2, 18 w 3 and 18 w 4 can also be referred to as an interface between the spacer 18 a and the gate 20. Each of the sidewalls 18 w 5, 18 w 6, 18 w 7 and 18 w 8 can also be referred to as an interface between the spacer 18 b and the gate 20.

The gate 20 includes a step structure defined by sidewalls 20 w 1 and 20 w 2. The gate 20 further includes another step structure defined by sidewalls 20 w 3 and 20 w 4. The gate 20 includes a step structure defined by sidewalls 20 w 5 and 20 w 6. The gate 20 further includes another step structure defined by sidewalls 20 w 7 and 20 w 8.

The portion of the gate 20 between the spacer 18 a and the spacer 18 b can be referred to as a tapered portion.

FIG. 2A is a simplified schematic cross-sectional view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 2A shows a semiconductor structure 300 according to certain embodiments of the present disclosure. The semiconductor structure 300 can also be referred to as a semiconductor device or a semiconductor apparatus.

As shown in FIG. 2A, the semiconductor structure 300 includes a substrate 10, a channel layer 12, a barrier layer 14, a dielectric layer 16, a gate 20, a drain 22 and a source 24. The semiconductor structure 100 further includes spacers 18 a and 18 b and protection layers 19 a and 19 b.

The semiconductor structure 300 shown in FIG. 2A is similar to the semiconductor structure 100 shown in FIG. 1A, except that the semiconductor structure 300 further includes protection layers 19 a and 19 b. The protection layer 19 a can be disposed between the dielectric layer 16 and the spacer 18 a. The protection layer 19 b can be disposed between the dielectric layer 16 and the spacer 18 b.

An interface 19 i 1 exists between the spacer 18 a and the protection layer 19 a. An interface 19 i 2 exists between the spacer 18 b and the protection layer 19 b. A length L1 represents the distance between the interface 19 i 1 and the interface 19 i 2. A length L2 represents the smallest distance between the spacer 18 a and the spacer 18 b. Referring to FIG. 2A, the length L2 is smaller than the length L1.

An enlarged view of the portion enclosed by the dotted rectangle C shown in FIG. 2A will be discussed in accordance with FIG. 2B. An enlarged view of the portion enclosed by the dotted rectangle D shown in FIG. 2A will be discussed in accordance with FIGS. 2C and 2D.

FIG. 2B is an enlarged view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 2B shows a portion of the semiconductor structure 300. Referring to FIG. 2B, the interface 18 i 1 between the gate 20 and the spacer 18 a can be a relatively rough surface. The interface 18 i 2 between the gate 20 and the spacer 18 b can be a relatively rough surface. An interface 20 i exists between the gate 20 and the barrier layer 14. The interface 20 i can also be a surface of the barrier layer 14. In some embodiments, the interface 20 i can be a substantially flat surface. In some embodiments, the interface 20 i can be a relatively smooth surface.

An interface 14 i exists between the protection layer 19 a and the barrier layer 14. In some embodiments, the interface 14 i can be coplanar with the interface 20 i.

FIG. 2C is an enlarged view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 2C shows a portion of the semiconductor structure 300 according to certain embodiments of the present disclosure. Referring to FIG. 2C, the interface 18 i 2 between the spacer 18 b and the gate 20 may be a relatively rough surface. The surface 16 s of the dielectric layer 16 may be a substantially flat surface. The surface 16 s of the dielectric layer 16 can be a relatively smooth surface. The relatively rough interface 18 i 2 can result from the etching process during the manufacturing of the semiconductor structure 300.

The protection layer 19 b may include a curved surface 19 s 1 located between the spacer 18 b and the dielectric layer 16. The curved surface 19 s 1 can result from the etching process during the manufacturing of the semiconductor structure 300.

Referring to FIG. 2C, the topmost portion of the spacer 18 b may not be coplanar with the surface 16 s. In some embodiments, the topmost portion of the spacer 18 b is lower than the surface 16 s. In some embodiments, a distance D3 exists between the topmost portion of the spacer 18 b and the surface 16 s.

Although FIG. 2C merely shows the structures/details around the spacer 18 b and the protection layer 19 b, it can be contemplated that the spacer 18 a and the protection layer 19 a may have features similar to those shown in FIG. 2C.

FIG. 2D is an enlarged view of a portion of a semiconductor structure according to certain embodiments of the present disclosure.

FIG. 2D shows a portion of the semiconductor structure 300 according to certain embodiments of the present disclosure. Referring to FIG. 2D, the interface 18 i 2 between the spacer 18 b and the gate 20 may be a relatively rough surface. The surface 16 s of the dielectric layer 16 may be a substantially flat surface. The relatively rough interface 18 i 2 can result from the etching process during the manufacturing of the semiconductor structure 300.

The protection layer 19 b may include a curved surface 19 s 2 located between the spacer 18 b and the dielectric layer 16. The curved surface 19 s 2 can result from the etching process during the manufacturing of the semiconductor structure 300.

Referring to FIG. 2D, the topmost portion of the spacer 18 b may not be coplanar with the surface 16 s. In some embodiments, the topmost portion of the spacer 18 b is higher than the surface 16 s. In some embodiments, a distance D4 exists between the topmost portion of the spacer 18 b and the surface 16 s.

Although FIG. 2D merely shows the structures/details around the spacer 18 b and the protection layer 19 b, it can be contemplated that the spacer 18 a and the protection layer 19 a may have features similar to those shown in FIG. 2D.

FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D and FIG. 3E illustrate a method of manufacturing a semiconductor structure according to some embodiments of the present disclosure.

The operations shown in FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D and FIG. 3E may be utilized to produce a semiconductor structure similar to the semiconductor structure 100 shown in FIG. 1A. The operations shown in FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D and

FIG. 3E may be utilized to produce a semiconductor structure similar to the semiconductor structure 200 shown in FIG. 1B.

Referring to FIG. 3A, a substrate 10 is provided, and a channel layer 12 is disposed on the upper surface of the substrate 10. A barrier layer 14 is then disposed on an upper surface of the channel layer 12. The polarization resulting from the heterojunction between the channel layer 12 and the barrier layer 14 forms a 2DEG region 13. In some embodiments, the 2DEG region 13 is formed within the channel layer 12. In some embodiments, the 2DEG region 13 is formed adjacent to the interface between the channel layer 12 and the barrier layer 14.

Referring to FIG. 3B, a dielectric layer 16 is disposed on the upper surface of the barrier layer 14. In some embodiments, the dielectric layer 16 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plating, and/or other suitable deposition steps.

A recess 16 h is formed on the dielectric layer 16. A recess 16 h is defined in the dielectric layer 16. The recess 16 h exposes a portion of the barrier layer 14. The recess 16 h exposes a surface 14 s of the barrier layer 14. In some embodiments, the recess 16 h can also be referred to as a trench.

The recess 16 h can be formed by, for example, a photolithography process. The recess 16 h can be formed by, for example, a photolithography machine. The recess 16 h can be formed by, for example, laser ablation or laser grooving, plasma dicing, wet etching or dry etching of grooves or trenches, and or laser induced cleaving/splitting. The recess 16 h can be formed by other suitable techniques.

Referring to FIG. 3C, a dielectric layer 18 is disposed on the dielectric layer 16. The dielectric layer 18 is disposed within the recess 16 h. The dielectric layer 18 is disposed on the surface 14 s of the barrier layer 14.

In some embodiments, the dielectric layer 18 may include materials identical to those of the dielectric layer 16. In some embodiments, the dielectric layer 18 may include materials different from those of the dielectric layer 16. In some embodiments, the dielectric layer 18 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plating, and/or other suitable deposition steps.

The dielectric layer 18 can be conformally formed above the dielectric layer 16 and the exposed barrier layer 14. The dielectric layer 18 includes a recess 18 r. The recess 18 r can also be referred to as a trench. The dielectric layer 18 has a thickness T1. The recess 18 r has a width L3. The thickness T1 of the dielectric layer 18 may influence the width L3 of the recess 18 r. In some embodiments, the width L3 of the recess 18 r decreases in response to an increase of the thickness T1 of the dielectric layer 18. The width L3 can also be referred to as a length L3.

Referring to FIG. 3D, the portions of the dielectric layer 18 above the dielectric layer 16 are removed and some portions of the dielectric layer 18 within the recess 16 h remain. The remaining portions of the dielectric layer 18 are then referred to as spacers 18 a and 18 b.

In some embodiments, the dielectric layer 18 can be removed, for example, by a dry etching technique. In some embodiments, the dielectric layer 18 can be removed, for example, by a dry blanket etching technique. The surface 16 s of the dielectric layer 16 is exposed after the dry etching process. The surface 16 s can be a relatively rough surface resulting from the dry etching process.

The spacer 18 a includes a curved surface 18 s 1. The spacer 18 b includes a curved surface 18 s 2. The surface 18 s 1 can be a convex surface. The surface 18 s 2 can be a convex surface. The surface 18 s 1 can be a relatively rough surface resulting from the dry etching process. The surface 18 s 2 can be a relatively rough surface resulting from the dry etching process.

The surface 18 s 1 may laterally connect the surface 16 s of the dielectric layer 16 to the surface 14 s of the barrier layer 14. The surface 18 s 1 may laterally connect between the surface 16 s of the dielectric layer 16 and the surface 14 s of the barrier layer 14. The surface 18 s 2 may laterally connect the surface 16 s of the dielectric layer 16 to the surface 14 s of the barrier layer 14. The surface 18 s 2 may laterally connect between the surface 16 s of the dielectric layer 16 and the surface 14 s of the barrier layer 14.

The spacer 18 a and the spacer 18 b define a recess 18 h. The recess 18 h can also be referred to as a trench. A length L1 is the top width of the recess 18 h. A length L2 is the bottom width of the recess 18 h. The length L2 can be the distance between the spacer 18 a and the spacer 18 b. The length L2 can be the width of the surface of the barrier 14 that is exposed by the spacers 18 a and 18 b.

The length L1 is greater than the length L2. The length of the recess 18 h decreases gradually from the top of the recess 18 h toward the bottom of the recess 18 h. The dimension of the recess 18 h decreases gradually from the top of the recess 18 h toward the bottom of the recess 18 h. The recess 18 h can also be referred to as a tapered recess.

The length L2 of the recess 18 h can correspond to the width L3 of the recess 18 r shown in FIG. 3C. In some embodiments, the length L2 of the recess 18 h decreases in response to a decrease of the width L3 of the recess 18 r, and vice versa. Therefore, the length L2 can be controlled by modifying the width L3 of the recess 18 r in the operation shown in FIG. 3C. Furthermore, the length L2 can be controlled by modifying the thickness T1 of the dielectric layer 18 in the operation shown in FIG. 3C.

Referring to FIG. 3E, a gate 20 is disposed on the dielectric layer 16, the spacers 18 a and 18 b, and the exposed surface of the barrier layer 14. In some embodiments, a portion of the gate 20 can be conformally disposed on the surface 18 s 1. In some embodiments, a portion of the gate 20 can be conformally disposed on the surface 18 s 2. In some embodiments, the surface 20 s 1 may include a curvature similar to that of the surface 18 s 1. In some embodiments, the surface 20 s 2 may include a curvature similar to that of the surface 18 s 2.

The surface 20 s 1 can be a convex surface. The surface 20 s 2 can be a convex surface.

A portion of the gate 20 within the recess 18 h comprises a length L1, another portion of the gate 20 within the recess 18 h comprises a length L2. The length L1 is greater than the length L2.

Since the top portion of the recess 18 h has a larger length L1, materials for forming the gate 20 can be easily disposed within the recess 18 h. The gate 20 can be integrally formed within the recess 18 h, without any cracks or discontinuity.

Referring back to FIG. 3B and FIG. 3D, the length L2 of the bottom of the recess 18 h is smaller than the length L1 of the bottom of the recess 16 h. As a result, the gate 20 disposed within the recess 18 h will have a smaller dimension near the exposed surface of the barrier layer 14. The gate 20 having a smaller dimension near the bottom of the recess 18 h enables the semiconductor structures 100 and 200 to work or operate in a higher frequency.

The operations described in accordance with FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D, and FIG. 3E provides a gate 20 having a smaller dimension near the bottom of the recess 18 h. The operations described in accordance with FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D, and FIG. 3E provides a semiconductor structure that can work in a higher frequency. The operations described in accordance with FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D, and

FIG. 3E provides a mechanism for forming a recess 18 h having a smaller bottom width, without the need of utilizing a photolithography machine with a higher precision.

FIG. 3F is a top view of a portion of a semiconductor structure according to certain embodiments of the present disclosure. FIG. 3F can be the top view of the semiconductor structure shown in FIG. 3D. The semiconductor structure shown in FIG. 3D can be a cross-sectional view along the dotted line E-E′ of FIG. 3F.

The semiconductor structure shown in FIG. 3F includes a dielectric layer 16, spacers 18 a and 18 b and a barrier layer 14. The spacer 18 a has a width L4, the spacer 18 b has a width L4, and the barrier layer 14 has a width L2. In some embodiments, the width L4 can be in a range of 60 nm to 80 nm. In some embodiments, the width L4 can be in a range of 80 nm to 100 nm. In some embodiments, the width L4 can be in a range of 100 nm to 120 nm. In some embodiments, the width L4 can be around 90 nm.

The length L2 can be less than 140 nm. The length L2 can be in a range of 120 nm to 140 nm. The length L2 can be in a range of 100 nm to 120 nm. The length L2 can be in a range of 80 nm to 100 nm. The length L2 can be in a range of 60 nm to 80 nm. The length L2 can be in a range of 40 nm to 60 nm. In some embodiments, the length L2 can be, for example, around 120 nm.

FIG. 3G is a top view of a portion of a semiconductor structure according to certain embodiments of the present disclosure. FIG. 3G can be the top view of the semiconductor structure shown in FIG. 3D. The semiconductor structure shown in FIG. 3D can be a cross-sectional view along the dotted line F-F′ of FIG. 3G.

Referring to FIG. 3G, the spacer 18 a may be a portion of a spacer 181. The spacer 18 b may be a portion of the spacer 181. The spacer 181 can include a portion 18 c connected between the spacers 18 a and 18 b. The spacer 181 can include a portion 18 d connected between the spacers 18 a and 18 b. The spacer 181 exposes a portion of the barrier layer 14. The spacer 181 surrounds the peripherals of the exposed portion of the barrier layer 14.

FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E and FIG. 4F illustrate a method of manufacturing a semiconductor structure according to some embodiments of the present disclosure.

The operations shown in FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E and FIG. 4F may be utilized to produce a semiconductor structure similar to the semiconductor structure 300 shown in FIG. 2A.

Referring to FIG. 4A, a substrate 10 is provided, and a channel layer 12 is disposed on the upper surface of the substrate 10. A barrier layer 14 is then disposed on an upper surface of the channel layer 12. The polarization resulting from the heterojunction between the channel layer 12 and the barrier layer 14 forms a 2DEG region 13. In some embodiments, the 2DEG region 13 is formed within the channel layer 12. In some embodiments, the 2DEG region 13 is formed adjacent the interface between the channel layer 12 and the barrier layer 14.

Referring to FIG. 4B, a dielectric layer 16 is disposed on the upper surface of the barrier layer 14. The dielectric layer 16 includes a recess exposing a surface of the barrier layer 14. A protection layer 19 is then disposed on the dielectric layer 16 and the exposed portion of the barrier layer 14.

The protection layer 19 may act as an etch stop layer. In some embodiments, the protection layer 19 may include aluminum oxide (Al₂O₃), silicon dioxide (SiO₂), silicon nitride (Si₃N₄) or any other appropriate materials. The protection layer 19 defines a recess 19 h.

Referring to FIG. 4C, a dielectric layer 18 is disposed on the protection layer 19. The dielectric layer 18 is disposed within the recess 19 h.

In some embodiments, the dielectric layer 18 may include materials identical to those of the dielectric layer 16. In some embodiments, the dielectric layer 18 may include materials different from those of the dielectric layer 16. In some embodiments, the dielectric layer 18 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plating, and/or other suitable deposition steps.

The dielectric layer 18 can be conformally formed above the protection layer 19. The dielectric layer 18 includes a recess 18 r. The recess 18 r can also be referred to as a trench. The dielectric layer 18 has a thickness T1. The recess 18 r has a width L3. The thickness T1 of the dielectric layer 18 may influence the width L3 of the recess 18 r. In some embodiments, the width L3 of the recess 18 r decreases in response to an increase of the thickness T1 of the dielectric layer 18.

Referring to FIG. 4D, the portions of the dielectric layer 18 above the protection layer 19 are removed and some portions of the dielectric layer 18 within the recess 19 h remain. The remaining portions of the dielectric layer 18 are then referred to as spacers 18 a and 18 b.

In some embodiments, the dielectric layer 18 can be removed, for example, by a dry etching technique. In some embodiments, the dielectric layer 18 can be removed, for example, by a dry blanket etching technique.

The surface 19 s 3 of the protection layer 19 is exposed after the dry etching process. The surface 19 s 4 of the protection layer 19 is exposed after the dry etching process. The surface 19 s 5 of the protection layer 19 is exposed after the dry etching process. The surface 18 s 1 can be a relatively rough surface resulting from the dry etching process. The surface 18 s 2 can be a relatively rough surface resulting from the dry etching process.

Referring to FIG. 4E, the portions of the protection layer 19 above the dielectric layer 16 are removed. The portion of the protection layer 19 above the barrier layer 14 is removed. The protection layer 19 may be removed by, for example, a wet etching process. The protection layer 19 may be removed by, for example, a wet etching process having high etching selectivity.

After a wet etching process, protection layers 19 a and 19 b remain. The protection layer 19 a includes a portion disposed between the spacer 18 a and the dielectric layer 16. The protection layer 19 a includes a portion disposed between the spacer 18 a and the barrier layer 14. The protection layer 19 b includes a portion disposed between the spacer 18 a and the dielectric layer 16. The protection layer 19 b includes a portion disposed between the spacer 18 a and the barrier layer 14.

The surface 16 s of the dielectric layer 16 can be a relatively smooth surface. The surface 14 s of the barrier layer 14 can be a relatively smooth surface.

The length L2 of the recess 19 h can correspond to the width L3 of the recess 18 r shown in FIG. 4C. In some embodiments, the length L2 of the recess 19 h decreases in response to a decrease of the width L3 of the recess 18 r, and vice versa. Therefore, the length L2 can be controlled by modifying the width L3 of the recess 18 r in the operation shown in FIG. 4C. Furthermore, the length L2 can be controlled by modifying the thickness T1 of the dielectric layer 18 in the operation shown in FIG. 4C.

Referring to FIG. 4D and FIG. 4E, the protection layer 19 may prevent the exposed portion of the barrier layer 14 from being lost during the dry etching process. The protection layer 19 may prevent a recess (for example, the recess 14 r of FIGS. 1B and 1C) from forming on the barrier layer 14. A recess on the barrier layer 14 may adversely affect the performance of the semiconductor device manufactured. A recess on the barrier layer 14 having a depth over a specific value may adversely affect the performance of the semiconductor device manufactured.

Referring to FIG. 4F, a gate 20 is disposed on the dielectric layer 16, the spacers 18 a and 18 b, the protection layers 19 a and 19 b, and the surface 14 s of the barrier layer 14.

In some embodiments, a portion of the gate 20 can be conformally disposed on the surface 18 s 1. In some embodiments, a portion of the gate 20 can be conformally disposed on the surface 18 s 2. In some embodiments, the surface 20 s 1 may include a curvature similar to that of the surface 18 s 1. In some embodiments, the surface 20 s 2 may include a curvature similar to that of the surface 18 s 2.

The gate 20 may include a recess 20 r. The gate 20 may include curved surfaces 20 s 1 and 20 s 2. The recess 20 r can be defined by the curved surfaces 20 s 1 and 20 s 2. The surface 20 s 1 can be a convex surface. The surface 20 s 2 can be a convex surface.

FIG. 5 is a simplified schematic cross-sectional view of a portion of a semiconductor structure according to certain comparative embodiments of the present disclosure.

FIG. 5 shows a semiconductor structure 500 according to certain comparative embodiments of the present disclosure. The semiconductor structure 500 can also be referred to as a semiconductor device or a semiconductor apparatus.

As shown in FIG. 5, the semiconductor structure 500 includes a substrate 10′, a channel layer 12′, a barrier layer 14′, a dielectric layer 16′, a gate 20′, a drain 22′ and a source 24′.

The dielectric layer 16′ includes a recess 16 h′ and a portion of the gate 20′ is disposed within the recess 16 h′. The recess 16 h′ has a length L1′. In some embodiments, the length L1′ can be larger than 250 nm. In some embodiments, the length L1′ can be, for example, around 300 nm. The length L1′ may influence the frequency characteristics of the semiconductor structure 500. A shorter length L1′ may enable the semiconductor structure 500 to work or operate in a higher frequency.

FIG. 6 is a simplified schematic cross-sectional view of a portion of a semiconductor structure according to certain comparative embodiments of the present disclosure.

FIG. 6 shows a semiconductor structure 600 according to certain comparative embodiments of the present disclosure. The semiconductor structure 600 can also be referred to as a semiconductor device or a semiconductor apparatus.

As shown in FIG. 6, the semiconductor structure 600 includes a substrate 10″, a channel layer 12″, a barrier layer 14″, a dielectric layer 16″, a gate 20″, a drain 22″ and a source 24″.

The dielectric layer 16″ includes a recess 16 h″ and a portion of the gate 20″ is disposed within the recess 16 h″. The recess 16 h″ has a length L1″. In some embodiments, the length L1″ can be smaller than 200 nm. In some embodiments, the length L1′ can be, for example, around 150 nm.

The length L1″ may influence the frequency characteristics of the semiconductor structure 600. A shorter length L1″ may enable the semiconductor structure 600 to work or operate in a higher frequency.

Nevertheless, due to the process or material limitations, the cost of forming a recess 16 h″ having a length L1″ smaller than a specific length increases. Also, due to the process or material limitations, disposing the gate 20″ within a recess 16 h″ having a length L1″ smaller than a specific length may induce some issues.

In some embodiments, the cost of forming a recess 16 h″ having a length L1″ smaller than 200 nm increases significantly. In some embodiments, the difficulty of forming the gate 20″ within the recess 16 h″ increases if the length L1″ is smaller than 200 nm.

Referring to FIG. 6, the gate 20″ includes portions 20 a″, 20 b″ and 20 c″. The portion 20 a″ may be separated from the portion 20 b″. The portion 20 a″ may not be electrically connected to the portion 20 b″. The portion 20 a″ may be separated from the portion 20 c″. The portion 20 a″ may not be electrically connected to the portion 20 c″. The gate 20″ may not function appropriately due to the separation between the portion 20 a″ and the portion 20 b″. The gate 20″ may not function appropriately due to the separation between the portion 20 a″ and the portion 20 c″. As a result, the semiconductor structure 600 may not function appropriately.

As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “lower,” “left,” “right” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present.

As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event of circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise. The term “substantially coplanar” can refer to two surfaces within micrometers (μm) of lying along a same plane, such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm of lying along the same plane. When referring to numerical values or characteristics as “substantially” the same, the term can refer to the values lying within ±10%, ±5%, ±1%, or ±0.5% of an average of the values.

The foregoing outlines features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A semiconductor device, comprising: a barrier layer; a dielectric layer disposed on the barrier layer and defining a first recess; a first spacer disposed on the barrier layer and within the first recess; a second spacer disposed on the barrier layer and within the first recess, wherein the first and second spacers are spaced apart from each other by a top surface of a portion of the barrier layer, wherein the top surface of the portion of the barrier layer is recessed; and a gate disposed on the barrier layer, the dielectric layer, and the first and second spacers, wherein the gate has a bottom portion located between the first and second spacers and making contact with the top surface of the portion of the barrier layer.
 2. The semiconductor device according to claim 1, wherein the recessed top surface of barrier layer forms a second recess filled with the bottom portion of the gate.
 3. The semiconductor device according to claim 2, wherein the second recess has a horizontal bottom surface in a position lower than an interface between the first spacer and the barrier layer and lower than an interface between the second spacer and the barrier layer.
 4. The semiconductor device according to claim 2, wherein the second recess has an inclined surface in a position lower than an interface between the first spacer and the barrier layer and lower than an interface between the second spacer and the barrier layer.
 5. The semiconductor device according to claim 2, wherein the second recess has a downward-extending surface, an inclined surface, and a horizontal bottom surface, wherein the inclined surface connects the downward-extending surface to the horizontal bottom surface.
 6. The semiconductor device according to claim 5, wherein the downward-extending surface has a first vertical depth, and the inclined surface has a second vertical depth greater than the first vertical depth.
 7. The semiconductor device according to claim 2, wherein the first and second spacers are spaced apart from each other by the second recess of the barrier layer.
 8. The semiconductor device according to claim 2, wherein the gate has a gate recess directly over the second recess of the barrier layer.
 9. The semiconductor device according to claim 2, wherein the gate extends across the first spacer from the second recess to a top surface of the dielectric layer.
 10. The semiconductor device according to claim 1, wherein each of the first and second spacers has a relatively rough surface in contact with the bottom portion of the gate.
 11. The semiconductor device according to claim 1, wherein the dielectric layer has a relatively rough surface in contact with the gate.
 12. The semiconductor device according to claim 1, wherein each of the first and second spacers has a relatively rough surface extending from a side of the dielectric layer to a region over the dielectric layer.
 13. The semiconductor device according to claim 1, wherein an interface formed between the first spacer and the bottom portion of the gate is curved.
 14. The semiconductor device according to claim 1, wherein the bottom portion of the gate has a bottom end in a position lower than the dielectric layer.
 15. The semiconductor device according to claim 1, wherein the bottom portion of the gate forms a horizontal interface with the top surface of the portion of the barrier layer.
 16. A semiconductor device, comprising: a barrier layer having a top surface and a first recess at the top surface; a first spacer disposed on the barrier layer and adjacent to the first recess a second spacer disposed on the barrier layer and adjacent to the first recess, wherein the first recess is located between the first and second spacers; a dielectric layer disposed on the barrier layer and away from the first recess such that the first and second spacers are closer to the first recess than the dielectric layer; and a gate disposed over the barrier layer, the dielectric layer, and the spacer, wherein the gate has a first portion extending from the first recess to the dielectric layer along the first spacer and a second portion extending from the first recess to the dielectric layer along the second spacer, such that the gate has a second recess between the first and second portions and over the first recess.
 17. The semiconductor device according to claim 16, wherein the first recess has a horizontal bottom surface in a position lower than an interface between the first spacer and the barrier layer and lower than an interface between the second spacer and the barrier layer.
 18. The semiconductor device according to claim 17, wherein the first recess has an inclined surface in a position lower than an interface between the first spacer and the barrier layer and lower than an interface between the second spacer and the barrier layer.
 19. The semiconductor device according to claim 16, wherein the first recess has a downward-extending surface, an inclined surface, and a horizontal bottom surface, wherein the inclined surface connects the downward-extending surface to the horizontal bottom surface.
 20. The semiconductor device according to claim 19, wherein the downward-extending surface has a first vertical depth, and the inclined surface has a second vertical depth greater than the first vertical depth. 